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Torsten Waaga
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DM9051: Single Chip SPI Fast Ethernet NIC Controller


The DM9051 is a fully integrated and cost-effective low pin count single chip Fast Ethernet controller with SPI, a 10/100M PHY and MAC, and 16K-byte SRAM. It is designed with low power and high performance process interface that support 3.3V with 5V IO tolerance.

The PHY of the DM9051 can interface to the UTP3, 4, 5 in 10Base-T and UTP5 in 100Base-TX with HP Auto-MDIX. It is fully compliant with the IEEE 802.3u Spec. Its Auto-Negotiation function will automatically configure the DM9051 to take the maximum advantage of its 10M or 100M abilities.
The DM9051 supports IEEE 802.3az in PHY and MAC to save power consumption when Ethernet is idle. The IEEE 802.3x Full-Duplex flow control and Half-Duplex back-pressure function also supported to avoid Ethernet packet loss with link partner.
The slave SPI is designed to support SPI clock mode 0 and 3 that compatible with the all master SPI interface of CPU. The clock speed can up to 50Mhz to co-operation with most high throughput master SPI.
The SPI burst command format is code-effective to minimize the command overhead in access DM9051(I) internal registers and packet data in memory.



No Description / Download Type Version Date Size
01 Davicom General Layout-Guide PDF 1.01 2011/05/05 719kB
02 Davicom Hardware Layout Guide PDF   2009/01/08 9,4M
03 Dacom Ethernet Design-In Guide PDF 1.00 2011/11/18 2,64M
04 Connecting 2 Davicom devices without transformers PDF   2007/12/11 76kB
05 Design hint Center-Tabs Transformer to PHY PDF   2011/02/02 305kB
06 Crystal Information PDF   2013/09/24 59kB
07 Programming-Reference-Flow-Chart PDF 1.00 2009/01/07 130kB

Part Specific:

11 DM9051 Demo Board Schematic PDF 2.1 2014/08/05 43kB
12 DM9051 Layout Guide PDF 1.1 2018/01/25 248kB