Trade Shows

26.02. - 28.02.2019, Nuremberg




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Germany / General
Torsten Waaga
✆: +49 (0) 2129 - 376-201
✉: Send email

Austria / Switzerland
Karl Eder
✆: +43 (0) 7448 - 21643-11
✉: Send email


DM9006: 2-Port Ethernet Switch Controller with 8/16-Bit processor Interface


The DM9006 is a fully integrated, high performance, and cost-effective fast Ethernet switch controller with one general processor bus interface, two ports 10M/100Mbps PHY. As a replacement for the DM9003 this part is completely pin- and software compatible for the DM9003. Additional features are IGMP v1, v2 snooping, IPv4 and IPv6 support, Port Security, Spanning Tree Protocol and Wake-on-LAN.
The general processor bus connect directly to internal host MAC with 8- or 16-bit data to access internal memory. The host MAC has the similar functions as other 10/100Mbps PHY or MII do. This makes the DM9006 act as an extended three ports switch and to shorten the latency from processor port to destination port.
The internal memory of the DM9006 supports up to 1K uni-cast MAC address table, and provide to two ports' and processor port's transmit and receive buffers. For efficient memory usage algorithm, a total of 48KB memory are shared with two ports and processor port in link list data structure. Each port of the DM9006 provides four priority transmit queues, that can be defined by port-based, 802.1p VLAN, or IP packet ToS field automatically, to fit the various bandwidth and latency requirement of data, voice, and video application. Each port also supports ingress and/or egress rate control to provide proper bandwidth. And up to 16 groups of 802.1Q VLAN with Tag/Un-tag functions are supported to provide efficient packet forwarding.
The TCP/UDP/IPv4 checksum generation and checking functions are also provided by processor port to offload the processor compute loading. Besides the packet transmit and receive functions, the processor port also provides various registers to control and get status of the DM9006 functional operation. Each port, include the processor port, provide the MIB counters and loop-back capability and the build in memory self test (BIST) for system and board level diagnostic. The integrated two ports PHY are compliant with IEEE 802.3u standards and support auto-MDI/MDIX for twisted pair cable transmit/receive direction switching automatically.