Trade Shows

26.02. - 28.02.2019, Nuremberg


DM9051: Single Chip SPI Fast Ethernet Controller



• 32 pin QFN Package
• current consumption 102mA + 40mA transformer
• 0.18 µm Process
• Slave SPI I/F with clock speeds up to 50MHz for high throughput applications
• Supports SPI clock mode 0 and 3
• Supports 10BASE-T, 100BASE-TX and 100M Fiber Interface
• Supports IEEE 802.3az Energy Efficient Ethernet (EEE)
• Supports wakeup frame, link status change and magic packet events for WOL
• Temperature Range: 0°C to 70°C and -40° to 85°C
• Integrated 3.3V to 1.8V low noise regulator
• Supports IPv4/TCP/UDP checksum generation and checking
• EEPROM interface to conficure chip settings
• 3.3V I/O with 5V tolerance
• Supports EMI (Class B) and HBM ESD Rating 8KV

Block Diagam DM9051

The DM9051 is a fully integrated and cost-effective low pin count single chip Fast Ethernet controller with SPI, a 10/100M PHY and MAC, and 16K-byte SRAM. It is designed with low power and high performance process interface that support 3.3V with 5V IO tolerance.

The PHY of the DM9051 can interface to the UTP3, 4, 5 in 10Base-T and UTP5 in 100Base-TX with HP Auto-MDIX. It is fully compliant with the IEEE 802.3u Spec. Its Auto-Negotiation function will automatically configure the DM9051 to take the maximum advantage of its 10M or 100M abilities.
The DM9051 supports IEEE 802.3az in PHY and MAC to save power consumption when Ethernet is idle. The IEEE 802.3x Full-Duplex flow control and Half-Duplex back-pressure function also supported to avoid Ethernet packet loss with link partner.
The slave SPI is designed to support SPI clock mode 0 and 3 that compatible with the all master SPI interface of CPU. The clock speed can up to 50Mhz to co-operation with most high throughput master SPI.
The SPI burst command format is code-effective to minimize the command overhead in access DM9051(I) internal registers and packet data in memory.